1. Technical Field
This disclosure relates to a technology of controlling a switching regulator constituting a DC-DC converter, and more particularly to a technology of controlling the switching regulator under light load conditions.
2. Description of the Related Art
The recent years have witnessed the increasing pervasiveness of compact mobile devices such as mobile phones. A compact secondary battery is used as the power source of such a compact mobile device. In order to reduce the size of the secondary battery and to maximize the usage time, attempts have been made to increase the performance of secondary batteries and to provide devices with higher energy saving capabilities.
The efficiency of a switching regulator constituting a DC-DC converter is an important factor in increasing the energy saving capabilities of a device. Typically, this efficiency is expressed by a function of the output current flowing to the load. The loss generated in accordance with the operation of the switching regulator accounts for a high percentage of the total power loss. Accordingly, the efficiency of the switching regulator declines when the load is light.
Conventionally, there have been many proposed techniques for improving the efficiency of a switching regulator under light load conditions. For example, to reduce the switching loss under light load conditions, there has been proposed a switching regulator that intermittently drives a PWM control circuit which is a control circuit for a duty cycle, under light load conditions (see, for example, patent document 1).
In this switching regulator, a predetermined upper limit voltage threshold and a predetermined lower limit voltage threshold are set. In the event that the output power is lower than the predetermined lower limit voltage threshold, the switch control circuit is configured to be turned off while the output voltage exceeds the lower limit voltage threshold.
When the output capacitor is discharged to a lower voltage level than the lower limit voltage threshold, the switch control circuit is activated once again, and causes the switch element to perform switching at a regular duty cycle, until the output voltage exceeds the upper limit voltage threshold. Subsequently, the switch control circuit stops operating until the output voltage falls below the lower limit voltage threshold. Accordingly, the output voltage is maintained within a range that is defined by the upper limit voltage threshold and the lower limit voltage threshold. These operations are repeatedly performed while the output power to the load is lower than the predetermined threshold. However, once the output power exceeds the predetermined threshold, the switching operation is resumed at a regular duty cycle. With such a configuration, the switching loss can be reduced under light load conditions, thereby improving the efficiency of the switching regulator.
FIG. 6 illustrates a circuit example of a conventional step-down switching regulator (see, for example, patent document 2).
The switching regulator shown in FIG. 6 has two feedback paths. The first feedback path uses a voltage VCNTL of a first feedback signal indicating a target maximum inductor current for maintaining an output voltage VOUT at a predetermined level. The voltage VCNTL of the first feedback signal is generated by comparing, with the use of an error amplifier 58, a division voltage VFB, which is obtained by dividing an output voltage VOUT with the use of a voltage dividing circuit including voltage dividing resistors R51 and R52, and a reference voltage VREF.
In the second feedback path, a voltage VS of a second feed back signal, which is a voltage between both ends of a sense resistor RS (=voltage VS of second feed back signal/inductor current IL), is detected. A comparator 56 compares the voltage VS of the second feedback signal and the voltage VCNTL of a first feedback signal. The comparator 56 generates a reset signal for achieving a cutoff status in which a switch 52 is turned off by resetting an RS flip-flop FF1, in the event that the voltage VS of the second feedback signal is higher than the voltage VCNTL of the first feedback signal. Preferably, the RS flip-flop FF1 operates in such a manner as to prioritize a reset input signal over a set input signal.
When the load current decreases, the voltage VCNTL of the first feedback signal drops below a light load reference voltage VLL, the output of a comparator 60 changes from a high level to a low level, and an AND circuit AND 1 outputs a low level signal. In such a light load condition, the current that flows from an output capacitor COUT to a load LOAD is significantly smaller than the current that flows by one inductor pulse. Therefore, the voltage VCNTL of the first feedback signal is maintained at a lower level than that of the light load reference voltage VLL, even after subsequent set signals have been generated by a set pulse generator 62. Accordingly, the output signals of the comparator 60 are maintained at a low level, and the RS flip-flop FF1 is maintained in a status where it is not set. Then, as the output voltage VOUT slowly declines and the voltage VCNTL of the first feedback signal exceeds the light load reference voltage VLL, the comparator 60 outputs a high-level signal. Accordingly, the RS flip-flop FF1 is set by the set pulse generated by the set pulse generator 62.
Subsequently, when the voltage VS of the second feedback signal becomes higher than the voltage VCNTL of the first feedback signal, the RS flip-flop FF1 is reset. With this process, the switching frequency of the switch 52 becomes low, so that high efficiency can be achieved even under light load conditions. This process cycle is repeated as long as the load is light. Furthermore, this process decreases the process frequency of the switch 52 when the load is light. Accordingly, the switching loss and driving loss of a power MOSFET can be reduced.
Patent Document 1: Japanese Laid-Open Patent Application No. H4-42771
Patent Document 2: Japanese Laid-Open Patent Application No. H10-225105
However, in the switching regulator for performing PWM control with the use of two feedback paths for the output voltage and the inductor current as illustrated in FIG. 6, it is known that the stability of the loop is degraded under conditions where the duty cycle exceeds 50%. Therefore, in order for the switching regulator to operate in a stable manner under any input/output condition, a small extent of slope compensation is preferably made on the internal loop.
In order to make such a slope compensation in the circuit shown in FIG. 6, a slope voltage needs to be added to the voltage VCNTL of the first feedback signal, or a slope voltage needs to be subtracted from the voltage VS of the second feedback signal. Furthermore, to achieve an appropriate slope voltage, the slope voltage needs to be a value greater than or equal to ½ (50%) of that of the down slope of the inductor (slope when switch is closed).
That is, the slope required for the circuit shown in FIG. 6 needs to be larger than (output voltage/inductance value×resistance value of sense resistor RS/2). Accordingly, in the event that the slope compensation is performed on the circuit shown in FIG. 6, the slope of the inductor current IL increases depending on the input voltage, when the switch 52 is turned on and in a conductive status. Therefore, under light load conditions, the peak current of the inductor current IL varies depending on the input voltage.
If the peak current of the inductor current IL is too low under light load conditions, the oscillatory frequency that is determined by the load increases, and the switching loss increases, thereby degrading the efficiency. Conversely, if the peak current is too high under light load conditions, the output current is larger than the current required for maintaining the output voltage VOUT at a predetermined value, thereby increasing ripples of the output voltage VOUT. Accordingly, under light load conditions, the peak current of the inductor current IL is preferably the peak current corresponding to a critical current.